Design IP

  • I/O
    PCIe, SRIO, Ethernet, USB2.0
  • Bridges
    PCIe/RIO to AXI/AHB
  • Memory / Storage
    Universal NVM Express Controller (UNEX) used for PCIe based SSDs and LPDDR2/3 controllers

Our Design IP cores are well tested in real designs and used in production. The blocks are fully synchronous and can be used in COT, FPGA, Gate Arrray, structured ASIC and Standard Cell designs.
Flexible user logic interface allows rapid connection to custom logic. Pre-Verification is done with Industry Standard VIP.
A synthesis environment and comprehensive documentation is part of the package. Language support is mainly Verilog HDL for IP‘s and System Verilog for the verification environment. Please check in for other language support. License options for example: single-use, multi-use, 5 year term.

DVCON 2015 | Munich | Nov. 11-12 

Avery Design: Stand Nr. E3